In modern digital integrated circuits, particularly those fabricated according to the well-known complementary metal-oxide-semiconductor (CMOS) technology, data output circuitry is generally implemented in the form of push-pull drive circuits. As is well known in the art, push-pull output drive circuits include two drive transistors; one drive transistor (the pull-up device) drives the output terminal toward the positive power supply voltage to effect a logic high level, while the second drive transistor (the pull-down device) drives the output terminal toward ground to effect a logic low level. In CMOS circuits, the pull-up device is generally implemented as a p-channel MOS transistor while the pull-down device is implemented as an n-channel MOS transistor. This configuration ensures that no DC current is drawn by the output driver. In addition, use of a p-channel pull-up device allows the output terminal to be driven fully to the power supply voltage, i.e., from "rail-to-rail", as there is no threshold voltage drop across the p-channel pull-up device (as there would be if the pull-up device were an n-channel transistor).
Most MOS integrated circuits fabricated over the last fifteen years have been powered from a nominal 5 volt power supply. However, with the advent of ultra thin gate dielectric layers used in the fabrication of modern MOS transistors, however, many recent integrated circuits are powered from a nominal 3.3 volt power supply. Since both types of circuits remain available and useful in modern digital systems, data must often be communicated from a 5 volt circuit to a 3.3 volt circuit over communication lines or buses. If all integrated circuits in the system were to utilize the same power supply bias, rail-to-rail output levels would be not only acceptable, but preferred. However, if mixed power supply devices are incorporated into the same system, care must be taken that a logic high level signal driven by a 5 volt device does not exceed 3.3 volts, to prevent damage to 3.3 volt devices receiving such a signal.
In such situations, it is desirable for the 5 volt device to provide an output high voltage level that meets an extremely stringent set of specification requirements. These requirements include a minimum logic high voltage level (V.sub.OH) of 2.4 volts and a maximum V.sub.OH of 3.3 volts, while providing 4 mA of source current in each condition, considering the specification variations of the 5 volt power supply the necessity to meet the specification for maximum and minimum output load conditions, all over an expected variation in manufacturing process parameters. In addition, particularly for integrated circuits in high performance systems, it is especially desirable to provide fast switching performance with minimum overshoot and undershoot (e.g., with settling times of less than 10 nsec), and with minimum circuit output impedance.
According to conventional design methodologies, these specification constraints may not be achievable, for circuits with typical process and voltage variations. For a V.sub.OH maximum voltage of 3.3 volts and a V.sub.OH minimum voltage of 2.4 volts, the total operating window (i.e., the difference therebetween) is 0.9 volts. According to typical modern design parameters, mere consideration of the maximum and minimum output load conditions (4 mA to 0 mA) translates to a reduction in the operating window of 0.75 volts. Variations in the power supply voltage will cause variations in the output driver reference voltage, typically generated by a resistor divider, reduces the operating window by another 0.30 volts. Minimum guardbanding on the V.sub.OH minimum level of 2.4 volts is typically 200 mV. Accordingly, even if one were to ignore the effect of process variations, the sum of the operating window reductions due to these factors is 1.25 volts, indicating that a V.sub.OH maximum of 3.3 volts is not achievable with conventional CMOS technology, even in the best case (i.e., no process variations).
For the output driver that drives a high output voltage to less than the power supply level, as would be the case for a 5 volt output driver driving a V.sub.OH maximum of 3.3 volts, an n-channel pull-up device may be used, and would be preferable due to the greater mobility of n-channel MOS transistors relative to p-channel MOS transistors. In this case, the gate voltage applied to the n-channel pull-up device (to turn it on) must be above the V.sub.OH minimum level by at least the threshold voltage of the device. It will be appreciated that an excessively high gate bias voltage on the pull-up device will limit the circuit options available for implementing the reduced V.sub.OH maximum output driver. While the required gate voltage could be reduced by either biasing the body node of the n-channel pull-up device to its source (i.e., to the output pad) or by using an n-channel pull-up device with a natural (non-implanted) threshold voltage, these options are undesirable, considering vulnerability of the circuit to latchup (in the case where V.sub.BS =0), and the instability and reduced reliability of natural V.sub.t transistors.
The combination of these factors has made difficult the design and implementation of output driver circuitry in which the operating window between V.sub.OH minimum and V.sub.OH maximum is limited. This difficulty is exacerbated by performance requirements of high switching speeds, and also by noise consideration in integrated circuits having as many as eighteen output switching simultaneously.
It is therefore an object of the present invention to provide output driver circuitry that can rapidly switch an output terminal, while maintaining a relatively small operating window for the high logic level output voltage.
It is another object of the present invention to provide such circuitry which is stable over variations in power supply voltage and process parameters.
It is another object of the present invention to provide such circuitry in which the threshold voltage of the driver transistors may be relatively high, to avoid vulnerability to latchup and other reliability degradation.
It is a further object of the present invention to provide such circuitry to allow a higher power supply voltage integrated circuit (e.g., 5 volts) to safely communicate data to an integrated circuit having a reduced power supply voltage (e.g., 3.3 volts).
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.